The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit suited for higher levels of integration and the circuit design of LSI and to a large scale integrated circuit (LSI) in which the above memory circuit and a logic circuit coexist.
In order to reduce the signal transmission delay between chips or between packages and to achieve quick access to a memory, both of a memory integrated circuit (memory IC) and a logic IC have hitherto been formed on one chip. Even in such an LSI including therein memories and logical gates, it has been desired to lower the manufacturing costs and time by using the masterslice method carried out in a logic LSI. The term "masterslice method" means a method in which circuit elements such as transistors and resistors are previously formed using common diffusion masks, and then different wiring patterns are formed between the circuit elements by replacing masks for wiring, thereby forming various kinds of LSI's. An LSI in which both memory and logic gate functions are integrated and the logic gate function is formed by the masterslice method is proposed in, for example, "ISSCC Digest of Technical Papers" 1979, pp. 64, 65 and 280. In such an LSI, however, the logic state portion can be formed by the masterslice method but the memory portion is built in the LSI, and therefore the degree of freedom with respect to each of the memory capacity and bit configuration is small. Since the memory portion and logical gate portion are formed independently of each other or circuit elements for memory and circuit elements for logical gates are formed independently of each other, there is a fair possibility of the utilization factor of each of the circuit element and chip area being lowered. Accordingly, the above LSI is not always favorable with respect to integration namely, packing density.